The Intel R&D Factory D1X has been expanded with a new module. Among other things, a new EUV with a high percentage of NA is being tested here. New machines required new buildings, so to speak, because they are bigger, heavier and above all higher. At the same time, Intel gave insight into further developments.
Research and development back in focus
An investment of $3 billion in an R&D plant is a staggering amount. The clean room area of the building called D1X is increased by just over 20 percent, but the new area has it all: in the new unit, not only are the upcoming classic EUV tools used, but the EUV with high NA is also being laid. The fact that new buildings are necessary for this should also be a problem for Intel factories around the world in the future.
So it is likely that the new Mod3 from the D1X will also be the blueprint to be implemented in future plants. After all, Intel is building several new factories over the next few years, and a complex in Magdeburg, Germany was also recently confirmed.
The plant will also test in the coming years if things do not go as planned with the High-NA EUV. Preparing for failure and having a plan B up your sleeve hasn’t been the forte of Intel lately. According to Intel, the backup plan already considered, which should also be able to carry out production steps with classic exposure to EUV, will come into effect in the near future. The processors likely to be affected are primarily the Intel 20A, but also the Intel 18A, which were pushed forward a bit recently and should be ready for serial production by 2025, just six months after the Intel 20A. Today it is said that Intel could close the gap until 2026 using traditional EUV lithography.
Intel states up to six years for the process to mature from the drawing board to the production chain. The Component Research Division (CR) is responsible for the first few years, with the manufacturing group joining only later.
In the end, of course, it’s all about the money. Here, the new Intel CEO recently pulled the checkbook and released more money to speed up the implementation. However, collaborating with partners and using tools that other manufacturers also use deviates from the previous lone wolf approach. A lot of what Intel does in factories isn’t fully compatible with other processes, and that starts with the design tools.
Don’t repeat the mistakes of the past
In statements to the press last week, it became clear that Intel does not want to repeat the mistakes of the past, especially those that led to the 10nm nightmare. What the manufacturer publicly presents as an innovation of the future looks very strange, because from the outside, such mechanisms were supposed to be effective in the past.
The fact that it didn’t do well later explains why 10nm failed so badly on the first try and why it took Intel years to get back on track. In the end, the only thing that helped was omitting half the targets at 10nm and starting from scratch. Intel also learned from this elsewhere: The technology roadmap’s timeline doesn’t say any year.
In the future, teams working on a process or technology for the new node should continue to accompany this technology in the future. There are also other teams that support and don’t have to quit once they’re planning something new. And with completely new processes, Intel no longer wanted to do everything at once in the future – which eventually broke the 10nm neck on the first try.
And so Intel still had to make the now overhauled and improved 10nm, even though it’s now sold as the Intel 7 in marketing. After 7 years of plan, which previously envisioned a very optimistic 10nm rendering in 2015. Because as it was said in 2012 by Intel: “We know how to make 10nm chipsThe next few years showed that this was not the case.
Internal intermediate process before PowerVia and GAA
This is best illustrated by the intermediate process that comes after Intel 3. It is not intended to produce any products, but is treated internally as an independent node. Intel is testing the new PowerVia on this using classic FinFETs. With this approach, it is almost impossible to have a large potential source of error besides the PowerVia to test. FinFETs have been around for over a decade, and it’s a proven technology. If problems arise, they should be attributed to PowerVia. Intel hopes the solution will be found more quickly.
Once development is complete, Gate-All-Around (GAA, Intel calls it RibbonFET) is introduced on the subsequent node. The first process that was implemented as such is the Intel 20A. But like many firsts of its kind, it will only be used in series for a short time under current plans. Intel 18A should follow as an improved variant within six months.
Ronler Acres transformed into Gordon Moore Park
Intel’s holdings in the United States are often named after what was once on the plot. In Hillsboro, Oregon, for example, there is Hawthorne Farm, and even the better known Jones farm, where not only technologies are developed, but events are uploaded – the computer base has also been used many times.
The Ronler Acres complex of factory buildings around the D1C, D1D and D1X and outbuildings used to follow this naming convention, but that is changing today. The entire complex will be renamed Gordon Moore Park in a ceremony today in honor of Intel’s greatest and most famous figure, Gordon Moore.
Intel has a total of 22,000 Hillsboro employees in four locations. According to its own data, more than US$52 billion has been invested in Oregon so far.
ComputerBase received information for this article from Intel under a non-disclosure agreement. The only requirement was the earliest possible publication date.
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